It has been discovered that the performance of a fin-shaped field effect transistor (or, fin-FET) and extremely thin silicon-on-insulator (or, ETSOI) semiconductor hardware can be improved with in-situ doped epitaxy and implant-free processes. However, integrating dual in-situ doped epitaxy for complementary metal oxide semiconductor (or, CMOS) structures can be a challenge for non-planar structures such as finFETs, tri-gate, and nanowire structures.
In particular, a hardmask is used to selectively grow the epitaxy in either the n-type field effect transistor (nFET) or the p-type FET (pFET) regions, while protecting the other device polarity (e.g., the other one of the nFET or the pFET). In order to improve device performance, the dielectric layer between the in-situ doped epitaxy layer and the channel (typically first spacer) is thinned as much as possible. In the current ETSOI CMOS process flow, a dielectric layer serves as the spacer on one device (e.g., nFET or pFET) polarity, while protecting the other device (the other one of the nFET or pFET) polarity during the epitaxy process.
A drawback of using this approach on non-planar finFET structures is that the process involves two separate spacer formation steps for nFET and pFET. These steps can complicate the formation of the finFET, as it may be challenging to remove the spacer material from fin sidewalls while retaining spacer material on gate sidewalls.
One conventional approach to address this issue is to utilize another hardmask layer, such as an oxide, to protect one device polarity during epitaxy on the other device. This approach, however, has disadvantages. For example, this approach involves using a thick dielectric layer due to the higher etch rate of oxide during epitaxy pre-clean. The use of a thicker dielectric creates patterning difficulties as the spacing between the transistors is made smaller in the future technology nodes. As such, these conventional approaches fail to address the above-noted deficiencies.